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www.lansdale.com page 1 of 26 ml145170 phase?requency detector pll frequency synthesizer with serial interface legacy device: motorola/freescale mc145170-2 pin connections tssop 16 = -7p plastic package case 948c 16 1 p dip 16 = ep plastic package case 648 so 16 = -5p plastic package case 751b 16 1 16 1 note : lansdale lead free ( pb ) product, as it becomes available, will be identified by a part number prefix change from ml to mle . cross reference/ordering information motorola package p dip 16 mc145170p2 ml145170ep so 16 MC145170D2 ml145170-5p tssop 16 mc145170dt2 ml145170-7p lansdale the lansdale ml145170 is a single?hip synthesizer capable of direct usage in the mf, hf and vhf bands. a special architecture makes this pll easy to program. either a bit?or byte?riented format may be used. due to the patented bitgrabber registers, no address/steering bits are required for random access of the three registers. thus, tuning can be accomplished via a 2?yte serial transfer to the 16-bit n register. the device features fully programmable r and n counters, an amplifier at the f in pin, on?hip support of an external crystal, a programmable ref- linear transfer functions (no dead zones). a configuration (c) register allows the part to be configured to meet various applications. a patented feature allows the c register to shut off unused outputs, thereby minimiz- ing noise and interference. in order to reduce lock times and prevent erroneous data from being whenever a new divide ratio is loaded into the n register, both the n and r counters are jam?oaded with their respective values and begin count- ing down together. the phase detectors are also initialized during the jam load. ? operating voltage range: 2.7 to 5.5 v ?operating temperature range: t a = ?0?to +85?c ? maximum operating frequency: 185 mhz @ v in = 500 mvpp, 4.5 v minimum supply 100 mhz @ v in = 500 mvpp, 3.0 v minimum supply ? operating supply current: 0.6 ma @ 3.0 v, 30 mhz 1.5 ma @ 3.0 v, 100 mhz 3.0 ma @ 5.0 v, 50 mhz 5.8 ma @ 5.0 v, 185 mhz ? r counter division range: 1 and 5 to 32,767 ? n counter division range: 40 to 65,535 ? direct interface to motorola spi serial data port ? see application notes an1207/d and an1671/d ? see web site www.lansdale.com for ml145170 control software bitgrabber is a trademark of motorola/freescale erence output, and both single and double?nded phase detectors with loaded into the counters, a patented jam load feature is included. issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 2 of 26 ml145170 block diagram thi s device cont a in s 4,800 a ctive tr a n s i s tor s . maximum ratings (volt a ge s referenced to v ss ) parameter symbol value unit dc s u pply volt a ge v dd ?0.5 to 5.5 v dc inp u t volt a ge v in ?0.5 to v dd + 0.5 v dc o u tp u t volt a ge v o u t ?0.5 to vdd + 0.5 v dc inp u t c u rrent, per pin i in 10 ma dc o u tp u t c u rrent, per pin i o u t 20 ma dc s u pply c u rrent v dd a nd v ss pin s i dd 30 ma power di ss ip a tion, per p a ck a ge p d 300 mw stor a ge temper a t u re t s tg ?65 to 150 c le a d temper a t u re, 1 mm from c as e for 10 s econd s t l 260 c notes: 1. m a xim u m r a ting s a re tho s e v a l u e s beyond which d a m a ge to the device m a y occ u r. f u nction a l oper a tion s ho u ld be re s tricted to the limit s in teh electric a l ch a r a cteri s tic s t a ble s or pin de s cription s s ection. thi s device cont a in s protection circ u itry to g ua rd a g a in s t d a m a ge d u e to high s t a tic volt a ge s or electric field s . however, pre- c au tion s m us t be t a ken to a void a pplic a tion s of a ny volt a ge higher th a n m a xim u m r a ted vol- t a ge s to thi s high?imped a nce circ u it. for proper oper a tion, v in a nd v o u t to the r a nge v ss (v in or v o u t ) vdd . un us ed inp u t s m us t a lw a y s be tied to a n a ppropri a te logic volt a ge level (e.g. either v ss or v dd ). un us ed o u tp u t s m us t be left open. should be constrained issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 3 of 26 electrical characteristics (volt a ge s referenced to v ss . t a = ?40 to 85c) parameter test condition symbol v dd v guaranteed limit unti power s u pply volt a ge r a nge v dd ? 2.7 to 5.5 v m a xim u m low-level inp u t volt a ge [note 1] (d in , clk, enb, f in ) dc co u pling to f in v 2.7 4.5 5.5 0.54 1.35 1.65 v (d in , clk, enb, f in ) dc co u pling to f in v ih 2.7 4.5 5.5 2.16 3.15 3.85 minim u m hy s tere s i s volt a ge (clk, enb) v hy s 2.7 5.5 0.15 0.20 (any o u tp u t) i o u t = 20 a v ol 2.7 5.5 0.1 0.1 (any o u tp u t) i o u t = ?20 a v oh 2.7 5.5 2.6 5.4 minim u m low-level o u tp u t c u rrent (pd o u t , ref o u t , f r , f v , ld, r , v ) v o u t = 0.3 v v o u t = 0.4 v v o u t = 0.5 v i ol 2.7 4.5 5.5 0.12 0.36 0.36 ma minim u m high-level o u tp u t c u rrent (pd o u t , ref o u t , f r , f v , ld, r , v ) v o u t = 2.4 v v o u t = 4.1 v v o u t = 5.0 v i oh 2.7 4.5 5.5 -0.12 -0.36 -0.36 ma minim u m low-level o u tp u t c u rrent (d o u t ) v o u t = 0.4 v i ol 4.5 1.6 ma m a xim u m high-level o u tp u t c u rrent (d o u t ) v o u t = 4.1 v i oh 4.5 -1.6 ma m a xim u m inp u t le a k a ge c u rrent (d in , clk, enb , osc in ) v in = v dd or v ss i in 5.5 1.0 a m a xim u m inp u t c u rrent (f in ) v in = v dd or v ss i in 5.5 150 a m a xim u m o u tp u t le a k a ge c u rrent (pd o u t ) v in = v dd or v ss . o u tp u t in high-imped a nce st a te i oz 5.5 100 (d o u t ) 5.5 5.0 a m a xim u m q u ie s chent s u pply c u rrent v in = v dd or v ss : o u tp u t s open; excl u ding f in amp inp u t c u rrent component i dd 5.5 100 a m a xim u m oper a ting s u pply c u rrent f in = 500 mvpp; osc in = 1.0 mhz @ 1.0 vpp; ld, f r , f v , ref o u t = in a ctive a nd no connect; osc o u t , v , r , pd o u t = no connect; d in , enb, clk = v dd or v ss i dd ? [note 2] ma notes: 1. when dc co u pling to the osc in pin i s us ed, the pin m us t be driven r a il?to?r a il, in thi s c as e, osc o u t s ho u ld be flo a ted. 2. the nomin a l v a l u e s a t 3.0 v a re 0.6 ma @ 30 mhz, a nd 1.5 ma @ 100 mhz. the nomin a l v a l u e s a t 5.0 v a re 3.0 ma @ 50 mhz, a nd 5.8 ma @ 185 mhz. the s e a re not g ua r a nteed limit s . il minimu m high-level inpu t volta ge [note 1] v v v v na m a xim u m low-level ou tpu t volta ge minimu m high-level ou tpu t volta ge issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 4 of 26 ac interface characteristics ( t a = ?40 to 85c, c l = 50 pf, inp u t t r = t r = 10 n s , u nle ss otherwi s e noted.) parameter symbol figure no. v dd v guaranteed limit unit seri a l d a t a clock freq u ency (note: refer to clock t w below) f clk 1 2.7 4.5 5.5 dc to 3.0 dc to 4.0 mhz m a xim u m prop a g a tion del a y, clk to d o u t t plh , t 1, 5 2.7 4.5 5.5 150 85 85 n s m a xim u m di sa ble time, d o u t active to high imped a nce t plz , t 2, 6 2.7 4.5 5.5 300 200 200 n s acce ss time, d o u t high imped a nce to active t pzh 2, 6 2.7 4.5 5.5 0 to 200 0 to 100 0 to 100 n s o u t cl = 50 pf t tlh , t 1, 5 2.7 4.5 5.5 150 50 50 n s cl = 200 pf 1, 5 2.7 4.5 5.5 900 150 150 n s m a xim u m inp u t c a p a cit a nce ? d in , enb , clk c in ? 10 pf m a xim u m o u tp u t c a p a cit a nce ? d o u t c o u t ? 10 pf timing requirements ( t a = ?40 to 85c, inp u t t r = t = 10 n s , u nle ss otherwi s e noted.) parameter symbol figure no. v dd v guaranteed limit unit in t su 3 2.7 4.5 5.5 55 40 40 minim u m set u p, hold, a nd recovery time s , enb v s clk t su , t h , t rec 4 2.7 4.5 5.5 135 100 100 n s minim u m in a ctive?high p u l s e width, enb t w(h) 4 2.7 4.5 5.5 400 300 300 n s minim u m p u l s e width, clk t w 1 2.7 4.5 5.5 166 125 125 n s t r , t f 1 2.7 4.5 5.5 100 100 100 s dc to 4.0 phl phz t m a ximu m ou tpu t tra n s i tion time, d minimu m setu p a nd hold times , d vs clk m a ximu m inpu t ris e a nd fa ll times , clk f ns h pzl thl , t issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 5 of 26 switching waveforms figure 1. figure 2. figure 3. figure 4. *includes all probe and fixtures capacitance. figure 5. test circuit *includes all probe and fixtures capacitance. figure 6. test circuit ? issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 6 of 26 loop specification ( t a = ?40 to 85c) figure v dd guaranteed range parameter test condition symbol no. v min max unit inp u t freq u ency, f in [note] v in 500 mvpp sine w a ve n co u nter set to divide r a tio s u ch th a t f 2.0 mhz f 7 2.7 3.0 4.5 5.5 5.0 5.0 25 45 80 100 185 185 mhz inp u t freq u ency, osc in extern a lly driven with ac?co u pled sign a l v in 1.0 v pp sine w a ve osc o u t = no connect r co u nter set to divide r a tio s u ch th a t f r 2 mhz f 8 a 2.7 3.0 4.5 5.5 1.0* 1.0* 1.0* 1.0* 22 25 30 35 mhz cry s t a l freq u ency, osc in a nd osc o u t c1 30 pf c2 30pf incl u de s str a y c a p a cit a nce f xtal 9 2.7 3.0 4.5 5.5 2.0 2.0 2.0 2.0 12 12 15 15 mhz o u tp u t freq u ency ref o u t c l = 30 pf f o u t 10, 12 2.7 4.5 5.5 dc dc dc ? 10 10 mhz oper a ting freq u ency of the ph as e detector s f 2.7 4.5 5.5 dc dc dc ? 20 20 mhz o u tp u t p u l s e width, r , v , a nd ld f r in ph as e with f v c l = 50 pf t w 11, 12 2.7 4.5 5.5 ? 20 16 ? 100 90 n s o u tp u t tr a n s ition time s , r , v , ld, f r , a nd f v c l = 50pf t tlh , t 11, 12 2.7 4.5 5.5 ? ? ? ? 65 60 n s in osc f in c in ? ? ? ? ? ? 7.0 7.0 pf * if lower freq u ency i s de s ired, us e w a ve s h a ping or higher a mplit u de s in us oid a l s ign a l in ac?co u pled c as e. al s o, s ee fig u re 22 for dc co u pling thl inpu t ca p a cita nce v issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 7 of 26 ? figure 7. test circuit f in *characteristic impedance ? figure 8a. test circuit, osc circuit externally driven [note] ? ? figure 8b. circuit to eliminate self?oscillation, osc circuit externally driven [note] ? figure 8. ? figure 9. test circuit, osc circuit with crystal figure 10. switching waveform figure 11. switching waveform *includes all probe and fixture capacitance. figure 12. test load circuit note: in pin when the ml145170 has power applied with no external signal. in . (self?oscillation is not harmful to the ml145170 and does not damage the ic.) applied at v use the circuit of figure 8b to eliminate self?oscillation of the osc issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 8 of 26 digital int e rfac e p ins din serial data input ( p in 5) the bit stream begins with the most significant bit (msb) and is shifted in on the low?o?igh transition of clk. the bit pattern is 1 byte (8 bits) long to access the c or configuration register, 2 bytes (16 bits) to access the n register, or 3 bytes (24 bits) to access the r register. additionally, the r register can be accessed with a 15?it transfer (see table 1). an optional pattern which resets the device is shown in figure 13. the values in the c, n, and r registers do not change during shifting because the transfer of data to the registers is con- trolled by enb. the bit stream needs neither address nor steering bits due to the innovative bitgrabber registers. therefore, all bits in the stream are available to be data for the three registers. random access of any register is provided (i.e., the registers may be accessed in any sequence). data is retained in the registers over a supply range of 2.7 to 5.5 v. the formats are shown in figures 13, 14, 15, and 16. d in typically switches near 50% of v dd to maximize noise immunity. this input can be directly interfaced to cmos devices with outputs guaranteed to switch near rail?o?ail. when interfacing to nmos or ttl devices, either a level shifter (mc74hc14a, mc14504b) or pull?p resistor of 1 to 10 k ? must be used. parameters to consider when sizing the resistor are worst?ase i ol of the driving device, maximum tolerable power consumption, and maximum data rate. clk serial data clock input ( p in 7) low?o?igh transistion on clock shift bits available at d in , out . the chips 16?/2?tage shift register is static, allowing clock rates down to dc in a continuous or intermittent mode. four to eight clock cycles followed by five clock cycles are needed to reset the device; this is optional. eight clock cycles are required to access the c register. sixteen clock cycles are needed for the n register. either 15 or 24 cycles can be used to access the r register (see table 1 and figures 13, 14, 15, and 16). for cascaded devices, see figures 24 to 31. clk typically switches near 50% of v dd and has a schmitt?riggered input buffer. slow clk rise and fall times are allowed. see the last paragraph of d in for more informa- tion. note to guarantee proper operation of the power?n reset (por) circuit, the clk pin must be held at the potential of either the v ss or v dd pin during power up. that is, the clk input should not be floated or toggled while the v dd pin is ramping from 0 to at least 2.7 v. if con- trol of the clk pin is not practical during power up, the e nb active?ow e nable input ( p in 6) this pin is used to activate the serial interface to allow the transfer of data to/from the device. when enb is in an inactive high state, shifting is inhibited, d out is forced to the high?mpedance state, and the port is held in the initialized state. to transfer data to the device, enb (which must start in and clk, and enb is taken back high. the low?o?igh transition on enb transfers data to the c, n, or r register depending on the data stream length per table 1. note transitions on enb must not be attempted while clk is high. this puts the device out of synchronization with the microcontroller. resynchronization occurs when enb is high and clk is low. of v dd , thereby minimizing the chance of loading erroneous data into the registers. see the last paragraph of d in for more information. d out three?tate serial data output ( p in 8) data is transferred out of the 16?/2?tage shift register through d out on the high?o?ow transition of clk. this out- put is a no connect, unless used in one of the manners dis- cussed below. d out could be fed back to an mcu/mpu to perform a wrap?round test of serial data. this could be part of a system check conducted at power up to test the integrity of the sys- finally, d out facilitates trouble shooting a system and per- mits cascading devices. r e f e r e nc e p ins osc in /osc out reference oscillator input/output ( p ins 1, 2) these pins form a reference oscillator when connected to terminals of an external parallel?esonant crystal. frequency setting capacitors of appropriate values as recommended by the crystal supplier are connected from each pin to ground (up to a maximum of 30 pf each, including stray capacitance). an external feedback resistor of 1.0 to 5.0 m ? is connected directly across the pins to ensure linear operation of the ampli- fier. the required connections for the components are shown in figure 9. if desired, an external clock source can be ac coupled to osc in . a 0.01 f coupling capacitor is used for measurement purposes and is the minimum size recommended for table 1. register access (msbs are shifted in first, c0, n0, and r0 are the lsbs) number of clocks accessed register bit nomenclature 9 to 13 8 16 15 or 24 other values 32 values > 32 see figure 13 c register n register r register none see figures 24 ? 31 (reset) c7, c6, c5,?, c0 n15, n14, n13,?, n0 r14, r13, r12,?, r0 p in d e scri p tions initialization sequence shown in figure 13 must be used. inactive high) is taken low, a serial transfer is made via d this input is also schmitt?riggered and switches near 50% tems processor, pc board traces, solder joints, etc. while high?o?ow transitions shift bits from d issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 9 of 26 applications. an external feedback resistor of approximately 5 m ? is required across the osc in and osc out pins in the ac?oupled case (see figure 8a or alternate circuit 8b). osc out is an internal node on the device and should not be used to drive any loads (i.e. osc out is unbuffered). however, the buffered ref out is available to drive external loads. the external signal level must be at least 1 v p?; the maxi- mum frequencies are given in the loop specifications table. these maximum frequencies apply for r counter divide ratios as indicated in the table. for very small ratios, the maximum frequency is limited to the divide ratio times 2 mhz. (reason: the phase/frequency detectors are limited to a maximum input frequency of 2 mhz.) if an external source is available which swings virtually rail?o?ail (v dd to v ss ), then dc coupling can be used. in the dc?oupled case, no external feedback resistor is needed. osc out must be a no connect to avoid loading an internal node on the device, as noted above. for frequencies below 1 mhz, dc coupling must be used . the r counter is a static counter and may be operated down to dc. however, wave shaping by a cmos buffer may be required to ensure fast rise and fall times into the osc in pin. see figure 22. each rising edge on the osc in pin causes the r counter to decrement by one. r e f out this output is the buffered output of the crystal?enerated reference frequency or externally provided reference source. this output may be enabled, disabled, or scaled via bits in the c register (see figure 14). ref out can be used to drive a microprocessor clock input, thereby saving a crystal. upon power up, the on?hip power?n?nitialize circuit forces ref out to the osc in divid- ed?y? mode. ref out is capable of operation to 10 mhz; see the loop specifications table. therefore, divide values for the reference divider are restricted to two or higher for osc in frequencies above 10 mhz. if unused, the pin should be floated and should be disabled via the c register to minimize dynamic power consumption and electromagnetic interference (emi). count e r out p ut p ins f r this signal is the buffered output of the 15?tage r counter. f r minimize interference with external circuitry. the f r signal can be used to verify the r counters divide ratio. this ratio extends from 5 to 32,767 and is determined by the binary value loaded into the r register. also, direct access to the phase detector via the osc in pin is allowed by choosing a divide value of 1 (see figure 15). the maximum frequency which the phase detectors operate is 2 mhz. therefore, the fre- quency of f r must not exceed 2 mhz. r signal appears as normally low and pulses high. the pulse width is 4.5 cycles of the osc in pin sig- selected, the osc in signal is buffered and appears at the f r pin. f v n counter output ( p in 10) f v can be enabled or disabled via the c register (patented). the output is disabled (static low logic level) upon power up. if unused, the output should be left disabled and unconnected to minimize interference with external circuitry. the f v signal can be used to verify the n counters divide frequency which the phase detectors operate is 2 mhz. therefore, the frequency of f v must not exceed 2 mhz. when activated, the f v signal appears as normally low and pulses high. loo p p ins f in frequency input ( p in 4) this pin is a frequency input from the vco. this pin feeds the on?hip amplifier which drives the n counter. this signal is normally sourced from an external voltage?ontrolled oscil- lator (vco), and is ac?oupled into f in . a 100 pf coupling mum size recommended for applications (see figure 7). the frequency capability of this input is dependent on the supply voltage as listed in the loop specifications table. for small ratio times 2 mhz. (reason: the phase/frequency detectors are limited to a maximum frequency of 2 mhz.) for signals which swing from at least the v il to v ih levels listed in the e lectrical characteristics table, dc coupling may be used. also, for low frequency signals, (less than the minimum frequencies shown in the loop specifications table), dc coupling is a requirement. the n counter is a static counter and may be operated down to dc. however, wave shaping by a cmos buffer may be required to ensure fast rise and fall times into the f in pin. see figure 22. each rising edge on the f in ment by 1. p d out single e nded p hase/frequency detector output ( p in 13) this is a three?tate output for use as a loop error signal tors dead zone has been eliminated. therefore, the phase/fre- quency detector is characterized by a linear transfer function. below and is shown in figure 17. pol bit (c7) in the c register = low (see figure 14) frequency of f v > f r or phase of f v leading f r : negative pulses from high impedance frequency of f v < f r or phase of f v lagging f r : positive pulses from high impedance frequency and phase of f v = f r ; essentially high?mpedance state; voltage at pin determined by loop filter pol bit (c7) = high nal, except when a divide ration of 1 is selected. when 1 is this signal is the buffered output of the 16?tage n counter. by the binary value loaded into the n register. the maximum reference frequency output ( pin 3) capacitor is used for measurement purposes and is the mini- ratio. this ratio extends from 40 to 65,535 and is determined divide ratios, the maximum frequency is limited to the divide pin causes the n counter to decre- can be enabled or disabled via the c register (patented). the unused, the output should be left disabled and unconnected to r counter output (pin 9) output is disabled (static low logic level) upon power up. if when activated, the f the operation of the phase/frequency detector is described when combined with an external low?ass filter. the detec- issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 10 of 26 frequency of f v > f r or phase of f v leading f r : positive pulses from high impedance frequency of f v < f r or phase of f v lagging f r : negative pulses from high impedance frequency and phase of f v = f r : essentially high?mpedance state; voltage at pin determined by loop filter out can be forced to the high?mpedance state by utilization of the disable feature in the c register r and v double e nded p hase/frequency detector outputs ( p ins 14, 15) these outputs can be combined externally to generate a loop error signal. through use of a motorola patented technique, the detectors dead zone has been eliminated. therefore, the phase/frequency detector is characterized by a linear transfer function. the operation of the phase/frequency detector is described below and is shown in figure 17. pol bit (c7) in the c register = low (see figure 14) frequency of f v > f r or phase of f v leading f r : v = neg- ative pulses, r = essentially high frequency of f v < f r or phase of f v lagging f r : v = frequency and phase of f v = f r : v and r remain essen- tially high, except for a small minimum time period when both pulse low in phase pol bit (c7) = high frequency of f v > f r or phase of f v leading f r : r = nega- tive pulses, v = essentially high frequency of f v < f r or phase of f v lagging f r : r = essen- tially high, v = negative pulses frequency and phase of f v = f r : v and r remain essen- tially high, except for a small minimum time period when both pulse low in phase these outputs can be enabled, disabled, and interchanged via the c register (patented) ld lock detector output ( p in 11) this output is essentially at a high level with narrow low?oing pulses when the loop is locked (f r and f v of the same phase and frequency). the output pulses low when f v and f r are out of phase or different frequencies (see figure 17). this output can be enabled and disabled via the c register (patented). upon power up, on?hip initialization circuitry dis- ables ld to a static low logic level to prevent a false ?ock signal. if unused, ld should be disabled and left open. p ow e r su pp ly v dd most p ositive supply p otential ( p in 16) this pin may range from 2.7 to 5.5 v with respect to v ss . for optimum performance, v dd should be bypassed to v ss using low?nductance capacitor(s) mounted very close to the device. lead lengths on the capacitor(s) should be minimized. (the very fast switching speed of the device causes current spikes on the power leads.) v ss most negative supply p otential ( p in 12) this pin is usually ground. for measurement purposes, the v ss pin is tied to a ground plane. note: thi s initi a liz a tion s eq u ence i s usua lly not nece ssa ry bec aus e the on?chip power?on re s et circ u it perform s the initi a liz a tion f u nction. however, thi s initi a liz a tion s eq u ence m us t be us ed immedi a tely a fter power u p if control of the clk pin i s not po ss ible. th a t i s , if clk (pin 7) toggle s or flo a t s u pon power u p, us e the a bove s eq u ence to re s et the device. 2.7 v, b u t not down to a t le as t 1 v (for ex a mple, the su pply drop s down to 2 v). thi s i s nece ssa ry bec aus e the on?chip power?on re s et i s only a ctiv a ted when the su pply r a mp s u p from a volt a ge below a pproxim a tely 1.0 v. figure 13. reset sequence essentially high, r = negative pulses h this output can be enabled, disabled, and inverted via the c (patented). register. if desired, pd als o, use this s equ ence if power is momenta rily interru pted such thhhhh hat the supply volta ge to the device is redu ced to below issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 11 of 26 figure 14. c register access and format (8 clock cycles are used) *at thi s point, the new byte i s tr a n s ferred to the c regi s ter a nd s tored. no other regi s ter s a re a ffected. c7?pol: select s the o u tp u t pol a rity of the ph as e/freq u ency detector s . when s et high, thi s bit invert s pd o u t a nd interch a nge s the r f u ntion with v as depicted in fig u re 17. al s o s ee the ph as e detector o u tp u t pin de s cription for more inform a tion. thi s bit i s cle a red low a t power u p. c6?pda/b: select s which ph as e/freq u ency detector i s to be us ed. when s et high, en a ble s the o u tp u t of ph as e/freq u ency detector a (pd o u t ) a nd di sa ble s ph as e/freq u ency detector b by forcing r a nd v r a nd v ) a nd ph as e/freq u ency detector a i s di sa bled with pd o u t forced to the high?imped a nce s t a te. thi s bit i s cle a red low a t power u p. c5?lde: en a ble s the lock detector o u tp u t when s et high. when the bit i s cle a red low, the ld o u tp u t i s forced to a s t a tic low level. thi s bit i s cle a red low a t power u p. c4?c2, osc2?osc0: reference o u tp u t control s which determine the ref o u t ch a r a cteri s tic s as s hown below. upon power u p, the bit s a re initi a lized su ch th a t osc in /8 i s s elected. c4 c3 c2 ref out frequency 0 0 0 dc (st a tic low) 0 0 1 osc in 0 1 0 osc in /2 0 1 1 osc in 1 0 0 osc in /8 (por def au lt) 1 0 1 osc in /16 1 1 0 osc in /8 1 1 1 osc in /16 c1?f v e: en a ble s the f v o u tp u t when s et high. when cle a red low, the f v o u tp u t i s forced to a s t a tic low level. the bit i s cle a red low u pon power u p. c0?f r e: en a ble s the f r o u tp u t when s et high. when cle a red low, the f r o u tp u t i s forced to a s t a tic low level. the bit i s cle a red low u pon power u p. /4 to the static high state. when cleared low, phase/frequency detector b is enabled ( issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 12 of 26 *at thi s point, the new data is transferred to the r regis ter and stored. no other registers are affected. figure 15. r register access and formats (either 24 or 15 clock cycles can be used) ?????? ??? issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 1 3 of 26 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? *at thi s point, the two new byte s a re tr a n s ferred to the n regi s ter a nd s tored. no other regi s ter s a re a ffected. in a ddition, the n a nd r co u nter s a re j a m?lo a ded a nd begin co u nting down together. figure 16. n register access and format (16 clock cycles are used) note: the pd o u t gener a te s error p u l s e s d u ring o u t?of?lock condition s . when locked in ph as e a nd freq u ency, the o u tp u t i s high imped a nce a nd o u t , r a nd v a re s hown with the pol a rity bit (pol) - low; s ee fig u re 14 for pol. figure 17. phase/frequency detectors and lock detector output waveform the volta ge a t tha t pin is determined by the low?pass filter ca p a citor. pd issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 14 of 26 crystal oscillator consid e rations the following options may be considered to provide a refer- ence frequency to lansdales/motorolas cmos frequency synthesizers. use of a hybrid crystal oscillator commercially available temperature?ompensated crystal oscillators (tcxos) or crystal?ontrolled data clock oscilla- tors provide very stable reference frequencies. an oscillator capable of cmos logic levels at the output may be direct or dc coupled to osc in . if the oscillator does not have cmos logic levels on the outputs, capacitive or ac coupling to osc in may be used (see figures 8a and 8b). on the world wide web. use of the on?hip oscillator circuitry the on?hip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source frequency. a fundamental mode crystal, parallel resonant at the desired operating frequency, should be connected as shown in figure 18. the crystal should be specified for a loading capacitance (c l ) which does not exceed 20 pf when used at the highest operating frequencies listed in the loop specifications table. larger c l values are possible for lower frequencies. assuming r1 = 0 ? , the shunt load capacitance (c l ) presented across the crystal can be estimated to be: the oscillator can be ?rimmed?on?requency by making a portion or all of c1 variable. the crystal and associated com- ponents must be located as close as possible to the osc in and osc out pins to minimize distortion, stray capacitance, stray inductance, and startup stabilization time. circuit stray capaci- tance can also be handled by adding the appropriate stray value to the values for c in and c out . for this approach, the term cstray becomes 0 in the above expression for c l . a good design practice is to pick a small value for c1 such as 5 o 10 pf. next, c2 is calculated. c1 < c2 results in a more robust circuit for start?p and is more tolerant of crystal parameter variations. power is dissipated in the effective series resistance of the crystal r e , in figure 20. the maximum drive level specified by the crystal manufacturer represents the maximum stress that the crystal can withstand without damage or excessive shift in operating frequency. r1 in figure 18 limits the drive level. the use of r1 is not necessary in most cases. to verify that the maximum dc supply voltage does not cause the crystal to be overdriven, monitor the output frequen- cy at the ref out pin (osc out is not used because loading impacts the oscillator). the frequency should increase very slightly as the dc supply voltage is increased. an overdriven crystal decreases in frequency or becomes unstable with an increase in supply voltage. the operating supply voltage must be reduced or r1 must be increased in value if the overdriven condition exists. the user should note that the oscillator start?p time is proportional to the value of r1. inverters, many crystal manufacturers have developed expertise in cmos oscillator design with crystals. discussions with such manufacturers can prove very helpful (see table 2). c l c in c o u t c in c o u t c a c s tr a y c1 c2 c1 c2 where c in = 5.0 pf ( s ee fig u re 19) c o u t = 6.0 pf ( s ee fig u re 19) c a = 1.0 pf ( s ee fig u re 19) c1 a nd c2 = extern a l c a p a citor s ( s ee fig u re 18) c s tr a y = c a p a cit a nce a ppe a ring a cro ss the cry s t a l termin a l s *m a y be needed in cert a in c as e s . see text. figure 18. pierce crystal oscillator circuit figure 19. parasitic capacitances of the amplifier and c stray figure 20. equivalent crystal networks note: v a l u e s a re su pplied by cry s t a l m a n u f a ct u rer (p a r a llel re s on a nt cry s t a l). for additional information about tcxos, visit freescale.com through the process of supplying crystals for use with cmos the total equivalent external circuit stray issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 15 of 26 technical note tn?4, statek corp. technical note tn?, statek corp. e. hafner, ?he piezoelectric crystal unit?efinitions and method of measurement? proc. ieee, vol 57, no. 2, feb. 1969 d. kemper, l rosine, ?uartz crystals for frequency control? electro?echnology, june 1969 p.j. ottowitz, a guide to crystal selection? electronic design, may 1966 d. babin, ?esigning crystal oscillators? machine design, march 7, 1985 d. babin, ?uidelines for crystal oscillator design? machine design, april 25, 1985 see web site lansdale.com for ml145170 software. table 2. partial list of crystal manufacturers cts corp. united st a te s cry s t a l corp. cry s tek cry s t a l st a tek corp. fox electronic s note: l a n s d a le c a nnot recommend one su pplier over a nother a nd in no w a y su gge s t s th a t thi s i s a complete li s ting of cry s t a l m a n u f a ct u er s . issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 16 of 26 phase?locked loop?low pass filter design (c) (a) 1 1 divided by 2. a c a p a citor c c i s then pl a ced from the midpoint to gro u nd to f u rther filter the error p u l s e s . the v a l u e of c c s ho u ld be su ch th a t the corner freq u ency of thi s network doe s not s ignific a ntly a ffect n . definitions: n = tot a l divi s ion r a tio in feedb a ck loop k (ph as e detector g a in) = v dd /4 volt s per r a di a n for pd o u t k (ph as e detector g a in) = v dd /2 volt s per r a di a n for v a nd r k vco (vco g a in) = 2 ? f vco ? v vco for a nomin a l de s ign s t a rting point, the us er might con s ider a d a mping f a ctor 0.7 a nd a n a t u r a l loop freq u ency n (2 f r /50) where f r i s the freq u ency a t the ph as e detector inp u t. l a rger n v a l u e s re su lt in f as ter loop lock time s a nd, for s imil a r s ideb a nd filtering,higher f r recommended reading: g a rdner, floyd m., phaselock techniques (second edition). new york, wiley?inter s cience, 1979. m a n ass ewit s ch, v a dim, frequency synthesizers: theory and design (second edition). new york, wiley?inter s cience, 1980. bl a nch a rd, al a in, phase?locked loops: application to coherent receiver design, new york, wiley?inter s cience, 1976. eg a n, willi a m f., frequency synthesis by phase lock, new york, wiley?inter s cience, 1981 rohde, ulrich, l., digital pll frequency synthesizers theory and design, englewood cliff s , nj, prentice?h a ll 1983. berlin, how a rd m., design of phase?locked loop circuits with experiments, indi a n a poli s , how a rd w. s a m s a nd co. 1978. ar254, ph as e?locked loop de s ign article s , motorol a semicond u ctor prod u ct s , inc., reprinted with permi ss ion from electronic design, 1987. an1207, the mc145170 in b as ic hf a nd vhf o s cill a tor s , motorol a semicond u ctor prod u ct s , inc., 1992. an1671, mc145170 pspice modeling kit, motorol a semicond u ctor prod u ct s , inc., 1998. (b) notes: 1. for (c), r i s frequ ently s plit into two s eries res i s tors ; ea ch res i s tor is equal to r 2. the r and v outputs swing rail?to?rail. therefore, the user should be careful not to exceed the common mode input range of the op a mp. 3. for the la tes t informa tion on mc33077 or equ iva lent, conta ct on semicondu ctor. an535, phase?locked loop des ign fu ndamenta l s , motorola semicondu ctor produ cts , inc. f a drhons , ja n, ?des ign a nd ana lyze plls on a progra mma ble ca lcu l a tor,? edn. ma rch 5, 1980. kinley, harold., the pll synthesizer cookbook , blu e ridge su mmit, pa, ta b books , 1980. ?rela ted vco s ideba nds . seidma n, arthu r h., integrated circuits applications handbook, cha pter 17, pp. 538-586. new york, john wiley & son s . issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 17 of 26 notes: 1. the r a nd v o u tp u t s a re fed to a n extern a l combiner/loop filter. see the ph as e?locked loop?low?p ass filter de s ign p a ge for a ddition a l inform a tion. the r a nd v o u tp u t s s wing r a il?to?r a il. therefore, the us er s ho u ld be c a ref u l not to exceed the common mode inp u t r a nge of the op a mp us ed in the combiner/loop filter. 2. for optim u m perform a nce, byp ass the v dd pin to v ss (gnd) with one or more low?ind u ct a nce c a p a citor s . 3. the r co u nter i s progr a mmed for a divide v a l u e = osc in /f r . typic a lly, f r i s the t u ning re s ol u tion req u ired for the vco. al s o, the vco freq u ency divided by f r = n, where n i s the divide v a l u e of the n co u nter. 4. m a y be a n r?c low?p ass filter. 5. m a y be a bipol a r tr a n s i s tor. figure 21. example application ml145170 issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 1 8 of 26 note: the s ign a l s a t point s a a nd b m a y be low?freq u ency s in us oid a l point s c a nd d, the s ign a l s a re cle a ned u p, h a ve s h a rp edge r a te s , a nd r a il?to?r a il s ign a l s wing s . with s ign a l s as de s cribed a t point s c a nd d, the ml145170 i s g ua r a nteed to oper a te down to a freq u ency as low as dc. refer to the mc74hc14a d a t a s heet for inp u t s witching level s a nd hy s tere s i s volt a ge r a nge. figure 22. low frequency operation using dc coupling ml145170 or square waves with slow edge rates or noisy signal edges. at issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 19 of 26 figure 23. input impedance at f in ? series format (r + jx) (5.0 mhz to 185 mhz) ? ? ? notes: 1. the 33 k ? re s i s tor i s needed to prevent the d in pin from flo a ting. (the d o u t pin i s a three? s t a te o u tp u t.) 2. see rel a ted fig u re s 25, 26, a nd 27. figure 24. cascading two ml145170 devices ml145170 ml145170 issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 20 of 26 ?????? ??? ?????? ??? figure 25. accessing the c registers of two cascading ml145170 devices figure 26. accessing the r registers of two cascading ml145170 devices note: at this point, the new data is transferred to the c regi sters of both devices and stored. no other registers a re affected. note: at this point, the new data is transferred to the r reigi sters of both devices and stored. no other registers are affected. issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 21 of 26 note: at this point, the new data is transferred to the n regi sters of both devices and stored. no other registers a re affected. figure 27. accessing the n registers of two cascaded ml145170 devices issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 22 of 26 ? notes: 1. the 33 k ? re s i s tor i s needed to prevent the d in pin from flo a ting (the d o u t pin i s a three? s t a te o u tp u t.) 2. thi s pll freq u ency synthe s izer m a y be a ml12210, ml12202, etc.,? 3. see rel a ted fig u re s 29, 30, a nd 31. figure 28. cascading two different device types ml145170 issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 2 3 of 26 ?????? ??? ?????? ??? figure 29. accessing the c registers of two different device types figure 30. accessing the a and r registers of two different device types note: at this point, the new data is transferred to the c regi sters of both devices and stored. no other registers a re affected. note: at this point, the new data is transferred to the a regi ster of device #2 and r register of device #1 and stored. no other regi sters are affected issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 24 of 26 ?????? ??? figure 31. accessing the r and n registers of two different device types note: at this point, the new data is transferred to the r regi ster of device #2 and n register of device #1 and stored. no other regi sters are affected. issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 25 of 26 tssop 16 = -7p plastic package case 948c-03 (ml145170-7p) issue b outline dimensions a b pin 1 identification l 18 9 16 d c g h f m k k1 j j1 section a?a a a 16x k ref -t- -u- -p- issue a
lan s dale s emiconductor, inc. ml145170 www.lansdale.com page 26 of 26 p dip 16 = ep plastic package case 648-08 (ml145170ep) issue r so 16 = -5p plastic package case 751b-05 (ml145170-5p) (sog-16) issue j outline dimensions -a- b f c s h g d j l m 16 pl k -t- f j m r x 45 g 8 pl p -b- -a- -t- d k c 16 pl lansdale s emiconductor reserves the right to make changes without further notice to any products herein to improve relia b ili- ty, function or design. lansdale does not assume any lia b ility arising out of the application or use of any product or circuit descri b ed herein; neither does it convey any license under its patent rights nor the rights of others. typical parameters which may b e provided in lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. all operating parameters, including typicals must b e validated for each customer application b y the customer?s technical experts. lansdale s emiconductor is a registered trademark of lansdale s emiconductor, inc. issue a

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